Complete RISC-V FPGA SoC Lab: 5 Items with Detailed Checklist
| Item | Lab Objective | Lab Content | Checklist / Notes |
|---|---|---|---|
| 1. C Program → Assembly Understanding | Understand how C programs are translated into RISC-V assembly, including ABI, stack layout, and function calls. | - Control structures: if / for / while - Typical algorithms: sorting, searching - Bit manipulation algorithms - MMIO and interrupt-handling in C programs |
- Verify stack frame layout and local variable allocation - Check function calls and return values - Observe compiler optimization effects (-O0 / -O2) - Explore recursion and function pointers in assembly |
| 2. ISA (Assembly → Binary) Understanding | Be able to read/write RISC-V instructions and understand the relationship between assembly and machine code. | - Basic instructions: arithmetic, immediate, comparison - Memory access: lw, sw, lbu - Control structures: for / while - Function calls and stack operations: jal, jalr, sw, lw - MMIO: store instructions - Interrupt instructions: CSR / mret - Integrated lab: LED blinking with timer interrupt in assembly |
- Verify CSR read/write operations - Optional: simple RV32I M-extension (mul/div) exercises - Perform instruction decoding / disassembly - Compare execution results with machine code |
| 3. HDL → Logic Design | Write CPU and peripheral circuits in Verilog and understand how they are converted into FPGA logic. | - Observe minimal PicoRV32 core - Create simple Verilog modules - Implement MMIO circuits in Verilog - Observe AXI4-Lite adapter integration - Explore BRAM implementation - Integrate PicoRV32 with peripherals - Design custom peripheral RTL → logic synthesis |
- Understand combinational vs sequential circuits - Understand clock/reset signals - Observe datapath and control path - Basic pipeline concepts (IF/ID/EX registers) |
| 4. Logic → FPGA Implementation | Implement logic on FPGA and test peripheral operation. | - LED blinking - 7-segment display / RGB LED bar - UART transmitter (check on PC terminal) - PWM LED brightness control - BRAM-based mini VRAM → HDMI display - PicoRV32 on FPGA - Mini SoC: CPU + GPIO + Timer + UART - Advanced: 5-stage pipeline CPU implementation - Final lab: integrate custom hardware + RISC-V application into SoC |
- Verify FPGA timing constraints (clock / timing reports) - Compare simulation waveform with actual FPGA operation - Verify I/O pin constraints - Debug with LED, UART, waveform analysis |
| 5. SoC Integration & Performance Evaluation | Integrate CPU, peripherals, bus, interrupts, and MMIO into a full SoC, and understand performance metrics and architecture differences. | - Study commercial SoC block diagrams (ARM Cortex-M / SiFive FE310 / ESP32) - Build minimal SoC (CPU + ROM + RAM) in HDL - Implement memory map & MMIO - Connect AXI / Wishbone bus - Implement Timer interrupts and UART control - Students design their own memory map - SoC integration & bare-metal operation - Compare pipeline CPU vs non-pipeline (CPI, throughput, hazards, branch prediction) - Final project: custom SoC development |
- Measure CPI and throughput - Count stalls and evaluate branch prediction hit rate - Analyze bus conflicts and wait states - Debug with UART / LED / waveform / simulation - Verify complete SoC operation |
✅ Features
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Complete learning path: C → Assembly → HDL → FPGA → SoC integration
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Clear objectives and checkpoints for each lab
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Includes advanced topics: pipeline CPU design, branch prediction evaluation
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Covers quantitative evaluation, debugging, and waveform analysis
If you want, I can also convert this into a step-by-step lab timeline with estimated durations for each task, which can serve as a full teaching schedule.
Do you want me to do that next?
| Step 1 | Write C programs (control structures, algorithms, bit operations) | - RISC-V GCC toolchain (gcc, objdump, readelf)- Text editor / IDE |
Compile C → assembly, view stack layout, ABI, local variables |
| Step 2 | Examine assembly / machine code | - riscv64-unknown-elf-as / ld- Spike / QEMU simulator - objdump |
Assemble / link / simulate; inspect instruction encoding and memory access |
| Step 3 | PicoRV32 minimal Verilog modules | - Verilog simulator (Icarus Verilog / ModelSim) - Yosys / Quartus synthesis |
Simulate RTL, observe registers, BRAM, combinational/sequential logic |
| Step 4 | Simple peripheral design (LED, 7-segment, MMIO) | - Verilog simulator - FPGA synthesis tool (Quartus for Tango Nano) - GTKWave / waveform viewer |
Implement peripherals, simulate, and observe logic behavior |
| Step 5 | UART / PWM / Mini SoC integration | - FPGA toolchain (Quartus) - Terminal software (PuTTY / Tera Term) - Oscilloscope / logic analyzer (optional) |
Verify UART communication, PWM control, LED outputs on FPGA |
| Step 6 | Minimal SoC (CPU + ROM + RAM + GPIO + Timer) | - FPGA toolchain - RISC-V GCC / Spike / QEMU - Waveform viewer |
Integrate CPU + memory + peripherals, run bare-metal programs, debug |
| Step 7 | MMIO + Timer + Interrupt lab | - FPGA toolchain - RISC-V toolchain - Terminal software |
Test memory-mapped I/O, configure timer interrupts, verify ISR execution |
| Step 8 | AXI / Wishbone bus integration | - FPGA synthesis / implementation tool - Simulation tool - Waveform viewer |
Connect CPU to peripherals via AXI/Wishbone, verify bus signals |
| Step 9 | Pipeline CPU / performance evaluation | - FPGA synthesis tool - RISC-V simulator (Spike) - Waveform viewer - Python / scripts for CPI calculation |
Compare pipeline vs non-pipeline CPU: CPI, stalls, branch prediction accuracy |
| Step 10 | Final SoC project (custom CPU + peripherals + RISC-V application) | - Full FPGA toolchain - RISC-V toolchain - Terminal software - Waveform viewer - Version control (Git) |
Integrate all components, run bare-metal programs, measure performance, document project |
ポイント
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GCC / RISC-V toolchainはステップ1〜10まで一貫して使用。
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Verilogシミュレーションはステップ3〜5とステップ8〜10で必須。
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**FPGAボード専用ツール（Quartus / programmer）**はステップ4以降、実機検証で必要。
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UART / LED / 波形解析はデバッグと動作確認に使用。
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Python / Git / scriptsは上級ステップの性能測定とプロジェクト管理に必要。
SoC実習 5項目まとめ
| 項目 | 実習目的 | 実習内容 |
|---|---|---|
| 1. Cプログラム → アセンブラ理解 | C言語からRISC-Vアセンブラへの変換過程を理解し、ABI・スタック・関数呼び出しの基本を学ぶ | - if / for / whileなどの制御構文 - ソート・探索などの典型アルゴリズム - ビット演算アルゴリズム - MMIOや割り込み対応のCプログラム作成 |
| 2. ISA（アセンブラ→バイナリ）理解 | RISC-V命令を「読める／書ける」状態にし、命令セットと機械語の対応を理解する | - 基礎命令（演算・即値・比較） - メモリアクセス（lw/sw/lbu） - 制御構文（for/while） - 関数呼び出し・スタック操作（jal/jalr） - MMIO（Store命令） - 割り込み命令（CSR/mret） - 総合課題：アセンブリでLED点滅＋Timer割り込み |
| 3. HDL → 論理回路設計 | VerilogでCPU・周辺回路を記述し、FPGA論理回路への変換を理解する | - PicoRV32の最小構成観察 - 簡単なVerilogモジュール作成 - MMIO回路設計と変換 - AXI4-Lite接続観察 - BRAM観察 - PicoRV32 + 周辺回路統合 - 学生独自周辺装置設計 → RTL → 論理回路化 |
| 4. 論理回路 → FPGA 実機 | 論理回路をFPGAに実装し、動作確認・周辺回路制御を体験する | - LED点滅 - 7セグメント表示 / RGBバー - UART送信器自作（PC確認） - PWMでLED明るさ調整 - BRAM利用（小型VRAM→HDMI表示） - PicoRV32搭載 - Mini SoC構築（CPU + GPIO + Timer + UART） - 上級：5段パイプラインCPU実装 - 最終：自作ハード + RISC-Vアプリ統合SoCプロジェクト |
| 5. SoC設計の統合理解・評価 | CPU・周辺回路・バス・割り込み・MMIOを統合したSoCを構築し、性能評価・設計理解を深める | - 商用SoCブロック図観察（ARM Cortex-M / SiFive FE310 / ESP32） - 最小SoC（CPU+ROM+RAM）HDL構築 - メモリマップ・MMIO実装 - AXI/Wishboneバス接続 - Timer割り込み・UART制御 - 学生設計のメモリマップ構築 - SoC統合・Bare-metal動作 - パイプラインCPU比較（CPI・スループット・ハザード・分岐予測） - 最終プロジェクト：オリジナルSoC開発 |