Icarus Verilog Simulator

Icarus Verilog (Simulation Tool)

Icarus Verilog is an open-source Verilog simulator that is widely used for RTL simulation before synthesis or FPGA/ASIC implementation. It provides a straightforward, command-line-based approach to simulating Verilog designs and generating waveforms for debugging.

Features of Icarus Verilog

  • Open-source and freely available

  • Can simulate Verilog (and some SystemVerilog) designs

  • Produces VCD (Value Change Dump) files for waveform analysis

  • Simple to set up and use for small to medium-sized designs

  • Fast compilation and simulation for quick testing of designs

Workflow with Icarus Verilog

  1. Write Verilog RTL (design files)

  2. Write Testbench (for simulation)

  3. Compile the Verilog files with iverilog

  4. Run the simulation with vvp

  5. Generate waveforms (optional, but recommended for debugging) using GTKWave

1️⃣ Writing the Verilog Design and Testbench

Before simulating with Icarus Verilog, you need the following:

  • Verilog RTL: This is your hardware design, e.g., a CPU core, a memory module, or any other component.

  • Testbench: This is a module that instantiates your design and provides test signals like clock, reset, and other inputs.

Example RTL (CPU design - cpu.v)

module cpu (
input clk,
input resetn,
output reg [31:0] pc
);

always @(posedge clk or negedge resetn) begin
if (!resetn)
pc <= 32'h0; // Reset PC to 0
else
pc <= pc + 4; // Increment PC on each clock cycle
end

endmodule

Example Testbench (for simulation - tb_cpu.v)

module tb;

reg clk = 0;
reg resetn = 0;
wire [31:0] pc;

// Instantiate the CPU module
cpu uut (
.clk(clk),
.resetn(resetn),
.pc(pc)
);

// Clock generation (50 MHz)
always #10 clk = ~clk;

// Test sequence
initial begin
// Open VCD dump file for waveform
$dumpfile("sim.vcd");
$dumpvars(0, uut);

// Reset the design
resetn = 0;
#20 resetn = 1; // Release reset after 20 time units

// Simulate for 1000 time units
#1000 $finish;
end

endmodule

2️⃣ Compile the Design with Icarus Verilog

You will use the iverilog command to compile both your RTL and testbench files into an executable simulation binary.

Command:

iverilog -o cpu_tb cpu.v tb_cpu.v

  • -o cpu_tb: Specifies the output file name for the simulation executable (in this case, cpu_tb).

  • cpu.v tb_cpu.v: These are the source Verilog files to be compiled.

3️⃣ Run the Simulation

Once compiled, you can run the simulation using the vvp command.

Command:

vvp cpu_tb

  • cpu_tb: This is the compiled simulation binary generated from iverilog.

  • This will execute the simulation and output results to the console.

4️⃣ Viewing Waveforms with GTKWave

To debug the design and see how internal signals change over time, it's helpful to generate a waveform file (VCD) and view it using GTKWave.

  1. In the testbench (tb_cpu.v), we included $dumpfile and $dumpvars commands to dump signals to a .vcd file.

  2. Run the simulation with vvp (as shown earlier).

  3. Open the VCD file using GTKWave:

Command:

gtkwave sim.vcd &

  • This will open GTKWave, allowing you to interactively explore the waveform of each signal.

5️⃣ Debugging with Waveforms

Inside GTKWave, you'll be able to see:

  • clk: The clock signal

  • resetn: The reset signal

  • pc: The program counter of the CPU

  • Other signals (like internal registers or memory) can also be added to the waveform for debugging.

You can zoom in on particular cycles to check how values change at different times.

Example of Simulation Output in GTKWave

  • Clock Signal (clk): This signal will toggle every 10 time units.

  • PC (pc): You will see the PC value increment by 4 (since each instruction is 4 bytes) after the reset is released.

This visualization helps you verify that the program counter (pc) is correctly incrementing, ensuring the core's basic functionality.

6️⃣ Summary of Icarus Verilog Workflow

Step Command Description
1. Write Verilog Design cpu.v RTL describing the design (e.g., CPU)
2. Write Testbench tb_cpu.v Testbench to apply inputs and check outputs
3. Compile with Icarus Verilog iverilog -o cpu_tb cpu.v tb_cpu.v Compile Verilog files into simulation executable
4. Run the simulation vvp cpu_tb Run the simulation and check console output
5. View waveforms gtkwave sim.vcd & Open waveform viewer to inspect signals over time

Benefits of Using Icarus Verilog

  • Fast and Lightweight: Great for quickly testing small to medium designs.

  • Free and Open-source: You can freely use and modify it for your needs.

  • Standard Verilog Support: Fully supports the Verilog language and provides decent SystemVerilog support as well.

  • Easy Integration with GTKWave: Allows you to visualize and debug waveforms.