Introduction

⭐ RISC-V FPGA SoC – Introductory Lecture Pack (1–2 hours)

designed for students who already learned the pieces (C, Verilog, FPGA) but do not yet understand the full system flow.

This pack includes:

  • Slide structure (20–25 slides)

  • Slide text (complete content per slide)

  • Lab exercises

  • Code references

  • Explanations in clear, beginner-friendly English

  • Focus on PicoRV32 + FPGA (e.g., Tang Nano 9K) using open-source tools only

You can copy/paste into PowerPoint or Google Slides directly.

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? RISC-V FPGA SoC – Introductory Lecture Pack

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? Slide 1 – Title

“From C Code to Hardware: How a RISC-V FPGA SoC Works”

An End-to-End Introduction

PicoRV32 + FPGA + Open-source Toolchain (Yosys/nextpnr)

? Slide 2 – Motivation

Students often know the parts, but not the system.

  • You learned C, assembly, FPGA, Verilog, memory, etc.

  • But these skills remain isolated islands.

  • To build a SoC, we need to connect the islands into one continuous flow.

? Slide 3 – Goal of This Lecture

After this 1–2 hour session, you will understand:

  • How C code becomes instructions

  • How instructions drive the PicoRV32 CPU

  • How the CPU accesses memory-mapped hardware

  • How Verilog peripherals interact with the bus

  • How everything runs on the FPGA device

This is the “big picture” of SoC development.

? Slide 4 – The Full Data Flow (Master Slide)

One diagram that explains everything:

[C Program]
↓ (RISC-V GCC)
[RISC-V Instructions]
↓ (Fetch/Decode/Execute)
[PicoRV32 Internal Logic: PC, ALU, Registers]
↓ (Memory bus: addr, data, wstrb)
[HDL Peripheral Modules]
↓
[FPGA Routing / IO Pins]
↓
[Real hardware: LED, UART, PWM]

We will revisit this diagram many times.

? Slide 5 – Why RISC-V?

  • Free and open ISA

  • Simple, clean, compact

  • Perfect for learning SoC design

  • Many FPGA-ready cores (PicoRV32, VexRiscv, CV32E40P, etc.)

  • Large industry adoption

? Slide 6 – The PicoRV32 CPU

• Small, simple, flexible

• Perfect for FPGA SoC education

Implements:

  • RV32I base ISA

  • Optional MUL/DIV

  • Optional interrupts

  • Simple memory bus (valid, addr, wdata, wstrb, rdata, ready)

This bus is the key to connecting C code and hardware.

? Slide 7 – Memory-Mapped I/O (MMIO)

The most important concept of SoC design.

The CPU sees peripherals as memory:

*(uint32_t*)0x03000000 = 1;

→ becomes a RISC-V sw instruction
→ CPU drives mem_addr=0x03000000
→ LED peripheral reacts
→ Physical LED turns ON

This is how software and hardware “talk.”

? Slide 8 – Minimal RISC-V Instructions Needed

You only need to understand 4 instructions to follow SoC behavior:

Purpose Instruction
arithmetic add
memory read lw
memory write sw
control flow beq / jal

These are the “bridge” between C and hardware.

? Slide 9 – Example: C → Assembly

C:

*LED = 1;

Assembly:

li a5,0x03000000
li a4,1
sw a4,0(a5)

Each instruction will appear in the waveform later.

? Slide 10 – The SoC Memory Map

Typical small FPGA RISC-V SoC:

0x0000_0000 – 0x0000_FFFF RAM
0x0300_0000 LED
0x0300_1000 PWM
0x0300_2000 UART

You will modify this map during the labs.

? Slide 11 – The System Bus (PicoRV32)

Important signals:

  • mem_valid

  • mem_addr

  • mem_wdata

  • mem_wstrb

  • mem_rdata

  • mem_ready

Lecture focus:
Only these signals are needed to understand SoC behavior.

? Slide 12 – HDL Peripheral Example (LED)

if (valid && addr==32'h0300_0000) begin
if (wstrb) led_reg <= wdata[0];
end

Simple, clean, effective.

? Slide 13 – HDL Peripheral Example (PWM)

if (addr==32'h0300_1000) duty <= wdata[7:0];
pwm_out = (counter < duty);

Shows how hardware behavior emerges from a memory write.

? Slide 14 – How C Controls Hardware

Summary:

  1. C writes a value

  2. RISC-V compiler generates sw

  3. CPU sends bus transaction

  4. HDL module receives it

  5. Hardware updates

  6. Physical device changes

This is the heart of SoC development.

? Slide 15 – Required Tools (OSS Only)

We use:

  • riscv32-unknown-elf-gcc (compile C to RISC-V)

  • Yosys (synthesis)

  • nextpnr-gowin (place & route)

  • openFPGALoader (write to board)

  • GTKWave (waveform viewing)

No Gowin IDE required.

? Slide 16 – Lab 0: Build the CPU + RAM + LED SoC

You build:

  • PicoRV32 core

  • RAM

  • LED register

  • Simple bus multiplexer

This SoC boots your compiled C program.

? Slide 17 – Lab 1: “Turn on the LED”

C code:

*(uint32_t*)0x03000000 = 1;
while (1);

Expected results:

  • LED lights

  • objdump shows sw

  • waveform shows mem_valid, mem_addr, wstrb

  • HDL LED register toggles

? Slide 18 – Lab 2: Add PWM Peripheral

Modify memory map:

0x0300_1000 → PWM duty

C code:

*PWM = d;

Expected:

  • FPGA pin outputs PWM

  • LED brightness increases/decreases

  • Waveform shows periodic comparison logic

? Slide 19 – Lab 3: Extend the SoC

Students add one new peripheral:

Ideas:

  • Timer

  • Button input

  • UART transmitter

  • Custom state machine

Goal:
Change the memory map and integrate new Verilog.

? Slide 20 – Understanding the Big Picture

Now students can trace the full path:

C → objdump → CPU bus → Verilog HW → FPGA → Physical signal

This is complete SoC understanding.

? Slide 21 – Debugging Workflow

To diagnose SoC problems:

  1. Check C

  2. Check objdump

  3. Check bus waveform

  4. Check HDL logic

  5. Check pin assignment

  6. Check physical hardware

Students learn to think like SoC developers.

? Slide 22 – The SoC Designer Mindset

You can now:

  • Add new hardware

  • Define new memory addresses

  • Write software to control them

  • Debug using waveforms

  • Think across software and hardware boundaries

This is the purpose of SoC education.

? Slide 23 – Summary

Today you learned:

  • RISC-V SoC architecture

  • Memory-mapped I/O

  • CPU bus transactions

  • HDL peripheral design

  • Full C→Hardware pipeline

  • How to extend a SoC

You now have the “big picture.”

? Slide 24 – Next Steps

Suggested learning paths:

  • UART, SPI, and I²C peripherals

  • Interrupt controllers

  • Custom accelerators

  • RISC-V privilege modes

  • Full OS (Zephyr / FreeRTOS / Linux-capable cores)

? Slide 25 – Questions

(Discussion slide)

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? Appendix A – Lab Code (C / Verilog / Makefile)

(identical to the previous assistant message, reusable)

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If you want, I can embed the full code directly into the slide deck appendix.

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? Optional Add-ons

I can also generate the following:

✔ Instructor notes for each slide
✔ Visual diagrams (bus, pipeline, memory map, waveform)
✔ Student worksheet (fill-in-the-blank)
✔ A printable “SoC flow cheat sheet”
✔ Lab instruction PDF
✔ Waveform screenshots (fake or generated)