RISC-V RV32I Base Instruction Set Overview
Word size: 32 bits
Registers: 32 general-purpose registers (x0–x31)
x0 is always zero
All instructions are 32 bits wide
1. Arithmetic Instructions (R-type and I-type)
| Mnemonic | Type | Operation | Description |
|---|---|---|---|
ADD rd, rs1, rs2 |
R | rd = rs1 + rs2 | Add |
SUB rd, rs1, rs2 |
R | rd = rs1 – rs2 | Subtract |
ADDI rd, rs1, imm |
I | rd = rs1 + imm | Add immediate |
SLT rd, rs1, rs2 |
R | rd = (rs1 < rs2)?1:0 | Set 1 if less than (signed) |
SLTU rd, rs1, rs2 |
R | rd = (rs1 < rs2)?1:0 | Set 1 if less than (unsigned) |
SLTI rd, rs1, imm |
I | rd = (rs1 < imm)?1:0 | Set 1 if less than immediate |
SLTIU rd, rs1, imm |
I | rd = (rs1 < imm)?1:0 | Unsigned version |
2. Logical Instructions
| Mnemonic | Type | Operation | Description |
|---|---|---|---|
AND rd, rs1, rs2 |
R | rd = rs1 & rs2 | Bitwise AND |
OR rd, rs1, rs2 |
R | rd = rs1 | rs2 | Bitwise OR |
XOR rd, rs1, rs2 |
R | rd = rs1 ^ rs2 | Bitwise XOR |
ANDI rd, rs1, imm |
I | rd = rs1 & imm | AND immediate |
ORI rd, rs1, imm |
I | rd = rs1 | imm | OR immediate |
XORI rd, rs1, imm |
I | rd = rs1 ^ imm | XOR immediate |
3. Shift Instructions
| Mnemonic | Type | Operation | Description |
|---|---|---|---|
SLL rd, rs1, rs2 |
R | rd = rs1 << (rs2[4:0]) | Shift left logical |
SRL rd, rs1, rs2 |
R | rd = rs1 >> (rs2[4:0]) | Shift right logical |
SRA rd, rs1, rs2 |
R | rd = rs1 >> (rs2[4:0]) (sign-extend) | Shift right arithmetic |
SLLI rd, rs1, shamt |
I | rd = rs1 << shamt | Shift left immediate |
SRLI rd, rs1, shamt |
I | rd = rs1 >> shamt | Shift right logical imm |
SRAI rd, rs1, shamt |
I | rd = rs1 >> shamt (sign-extend) | Shift right arithmetic imm |
4. Load Instructions (I-type)
| Mnemonic | Type | Operation | Description |
|---|---|---|---|
LB rd, offset(rs1) |
I | Load byte (sign-extend) | 8 bits |
LH rd, offset(rs1) |
I | Load halfword (sign-extend) | 16 bits |
LW rd, offset(rs1) |
I | Load word | 32 bits |
LBU rd, offset(rs1) |
I | Load byte unsigned | 8 bits |
LHU rd, offset(rs1) |
I | Load halfword unsigned | 16 bits |
5. Store Instructions (S-type)
| Mnemonic | Type | Operation | Description |
|---|---|---|---|
SB rs2, offset(rs1) |
S | Store byte | |
SH rs2, offset(rs1) |
S | Store halfword | |
SW rs2, offset(rs1) |
S | Store word |
6. Branch Instructions (B-type)
| Mnemonic | Type | Operation | Description |
|---|---|---|---|
BEQ rs1, rs2, label |
B | if (rs1 == rs2) branch | |
BNE rs1, rs2, label |
B | if (rs1 != rs2) branch | |
BLT rs1, rs2, label |
B | if (rs1 < rs2) branch (signed) | |
BGE rs1, rs2, label |
B | if (rs1 ≥ rs2) branch (signed) | |
BLTU rs1, rs2, label |
B | if (rs1 < rs2) branch (unsigned) | ignore sign bit |
BGEU rs1, rs2, label |
B | if (rs1 ≥ rs2) branch (unsigned) | ignore sign bit |
7. Jump and Link Instructions
| Mnemonic | Type | Operation | Description |
|---|---|---|---|
JAL rd, label |
J | rd = PC+4; PC = label | Jump to label and load PC+4 to rd |
JALR rd, offset(rs1) |
I | rd = PC+4; PC = rs1 + offset | Jump and link register |
8. Upper Immediate Instructions (U-type)
| Mnemonic | Type | Operation | Description |
|---|---|---|---|
LUI rd, imm20 |
U | rd = imm20 << 12 | Load upper immediate 20 bits (lower 12 bits 0) |
AUIPC rd, imm20 |
U | rd = PC + (imm20 << 12) | Add upper immediate to PC 20 bits (lower 12 bits 0) |
9. System Instructions
| Mnemonic | Type | Description |
|---|---|---|
ECALL |
System | Environment call (system call) |
EBREAK |
System | Breakpoint for debugger |
FENCE |
System | Memory ordering fence |
CSRRS, CSRRW, etc. |
System | Control and status register access (privileged) |
Register Summary (RV32I)
| Register | ABI Name | Description |
|---|---|---|
| x0 | zero | Constant 0 |
| x1 | ra | Return address |
| x2 | sp | Stack pointer |
| x3 | gp | Global pointer |
| x4 | tp | Thread pointer |
| x5–x7 | t0–t2 | Temporaries |
| x8 | s0/fp | Saved register / frame pointer |
| x9 | s1 | Saved register |
| x10–x17 | a0–a7 | Function arguments / return values |
| x18–x27 | s2–s11 | Saved registers |
| x28–x31 | t3–t6 | Temporaries |
Summary:
-
RV32I = 47 core instructions
-
Clean, orthogonal design (regular formats)
-
Easy to decode and ideal for hardware or teaching CPU design